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adms: A code generator for the Verilog-AMS language
ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile C code for the API of spice simulators. Based on transformations specified in XML language, ADMS transforms Verilog-AMS code into other target languages.
Name: | adms |
Release: |
2.3.7-2mamba |
Architecture: | x86_64 |
Group: | Applications/Scientific |
Size: | 287,42 kB |
Upstream URL: | https://sourceforge.net/projects/mot-adms/ |
Source RPM: | adms |
Brothers | Provides | Obsoletes | Requires | Recommends |
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adms-debug
| adms = 0:2.3.7-2mamba adms(x86-64) = 0:2.3.7-2mamba
| | libc.so.6(GLIBC_2.34)(64bit) [1] libm.so.6()(64bit) [1] rtld(GNU_HASH) [1]
| |
Provided files/usr/bin/admsCheck
/usr/bin/admsXml
/usr/include/adms
/usr/include/adms/constants.vams
/usr/include/adms/disciplines.vams
/usr/lib/.build-id
/usr/lib/.build-id/10
/usr/lib/.build-id/10/5be2f7c52d645c48d70918b35aac029a7dd9a6
/usr/lib/.build-id/46
/usr/lib/.build-id/46/0c3f68062d7f8f33b97b31c74589907218847c
/usr/share/doc/adms-2.3.7
/usr/share/doc/adms-2.3.7/AUTHORS
/usr/share/doc/adms-2.3.7/COPYING
/usr/share/man/man1/admsCheck.1.gz
/usr/share/man/man1/admsXml.1.gz